Clock Management with PLLs and DLLs By Bob Kirk Here's a look at design strategies for dealing with different clock management situations.

ASIC Implementation in Programmable Logic By Thomas Philbin The re-targeting of an ASIC design into an FPGA demonstrates the viability of using programmable logic in signal processing applications. SOCs and Embedded Programmable Logic By Yankin Tanurhan Actel reports that it has developed an embeddable reprogrammable gate array that will support the complexity needed by SOC designers. Developing an Emulation Environment By Cinda Flynn Verification continues to ravage time and energy resources in the design team. Alternative therapies are coming to the rescue. Focus Report: Design Libraries By Peggy Aycinena

Editorial By Peggy Aycinena Beauty and the Benchmark Inside SOCs By Steve Winegarden A Platform-based Design Approach for Configurable SOCs Inside Test By L.T. Wang, Jaehee Lee, and Hsin-Po Wang The New Testability Sins: Don't Atone, Avoid! Viewpoint By Red Wiebe It's all in the Acronyms

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